1. Field of the Invention
The invention relates to delay-locked loops and clock generation, and in particular to false lock protection circuitry incorporated in delay-locked loops.
2. Background of the Invention
A delay-locked loop (DLL) processes a reference clock signal (Dref) to generate a sequence of delayed clock signals. The frequency and period of the reference clock signal Dref are the same as those of each of the generated clock signals however each delayed clock signal is phase shifted by a common delay period (Δt) from the previous delayed clock signal. When operating properly, the DLL provides delayed clock signals with positive edge transitions that span a single period of the reference clock signal Dref. Initially, the delay period Δt might not be set to provide such properly spaced delayed clock signals spanning one and only one period of the reference clock signal Dref. During initial acquisition, the DLL uses a feedback signal to adjust the delay period Δt until the DLL converges and locks to an appropriate fixed delay period. Over time, the fixed delay period results in a sequence of delayed clock signals that may or may not span a single period of the reference clock signal.
When the DLL converges on an improper delay period, it is falsely locked. In this case, the delayed clock signals may span more than one period of the reference clock signal if the delay period Δt is too long. Alternatively, the delayed clock signals may span a small fraction of one period of the reference clock signal if the delay period Δt is too short.
One solution to determine if a DLL is falsely locked with an improper delay period is to apply all of the delayed clock signals to some combinational logic to determine if the delayed clock signals properly span one period of the reference clock signal Dref. Combinational logic processing all of the delayed clock signals may allow a DLL to determine whether the DLL is falsely locked to a delay period that is either too long or too short.
Using all of the delayed clock signals, however, results in additional noise produced by the signals' combined high-low and low-high transitions. That is, noise may be an unwanted byproduct of a combinational logic processing a multitude of phases of the reference clock signal. This noise results from unintentional mixing of signals having a slightly different phase.
Thus, false lock protection circuitry may cause unwanted interfering noise at harmonics of the reference clock frequency. Therefore, a need exists to reduce noise generated by conventional false lock protection circuitry.